Part 4...Demos using Java Applets

~ELECTRONICS~

Part 4

Complex gates

As in NMOS technology, there are certain logic functions that can be realized very efficiently by CMOS gates. These gates are called complex gates because they realize a complex logic function - although the gates themselves are rather simple.

Typical example for complex gates found in almost all cell libraries are combinations of AND-OR-INVERT and OR-AND-INVERT gates.
For example, the gate for the logic function Y = !((A ^ B) | (C ^ D ^ E)) - that is, the NOT of the OR of two ANDs - is typically called an AOI32 gate. This gate is shown in the next applet. It needs 10 transistors only (5 pairs of N-type and P-type transistors, one pair for each input).

To simplify the circuit schematic, the input wires are not drawn completely. Rather, all input wires are broken into two pieces, connected to the corresponding N-type and P-type transistors. For example, to toggle the input voltage for input A, you can click both near the N-type or the P-type transistor gate connected to input A.

Note that again the N-type and P-type paths in this gate are complementary. P-type transistors connected in series correspond to N-type transistors connected in parallel, and vice versa.

The generalization to other complex gates should be obvious. Again, gates with more than three transistors connected in series are not used. Most cell libraries contain gates from AOI21 and OAI21 up to aOI33 and OAI33. Try to construct one of these on paper and understand how it works!

The CMOS transmission gate

The first applet on this page demonstrated the switching behaviour of N-type and P-type transistors. However, while both N-type and P-type transistors indeed have a very large resistance between source and drain when switched off, a detailed analysis reveals that the resistance between source and drain depends on the source and drain voltages when switched on. Especially, there is a voltage drop across a conducting N-type transistor when the source voltage is near VCC, and a voltage drop across a conducting P-type transistor when its source voltage is near GND. (Note that thhis poses no problem in the static CMOS gates, where all source contacts of N-type transistors are connected to GND and all source contactes of P-type transistors are connected to VCC.)

Therefore, the use of single N-type or P-type transistors as switches is limited to circuits, where the voltage drop across the conducting transistors is not critical. A series connection of transistors used as switches is usually not possible in digital circuits.

But a combination of N-type and P-type transistors allows to realize efficient switches in CMOS technology. The circuit consists of one N-type and one P-type transistor connected in parallel and controlled by inverted gate voltages. This circuit, called a transmission gate (T-gate) is demonstrated in the following applet:

Click on the gate of either the N-type or the P-type transistor to invert (both) gate voltages. A T-gate requires that the N-type and P-type transistors have inverted gate voltages.
Click on the 'L' (source) or 'R' (drain) contacts to toggle the corresponding voltage from GND to VCC to Z.

To better demonstrate the switching behaviour of the T-gate, the new voltage just selected by clicking 'wins' over a previously selected.

If the gate voltage of the N-type transistor is '0', the P-type transistors has a gate voltage of '1' and both transistors are nonconducting. On the other hand, if the gate voltage of the N-type transistor is '1' and the gate voltage of the P-type transistor is '0', both transistors are conducting. If the source voltage is near VCC, there is a voltage drop across the N-type transistor but (almost) no voltage drop across the P-type transistor. If the source voltage is near GND, the N-type transistor has (almost) no voltage drop. Because of the symmetry of standard MOS transistors, there is no reason to differantiate between source and drain in a T-gate. The contacts are therefore usually called 'L' (left) and 'R' (right).

The CMOS D-latch with T-gates

In CMOS technology, T-gates allow efficient realizations of several important logical functions. Perhaps the most important use is demonstrated in the next applet. A standard D-latch (level controlled flipflop) can be build from four 2-input NAND gates. Therefore, 16 transistors are needed for one D-latch. (Try to construct this circuit on paper - the simple D-latch circuit is one of our pet examination problems!)

The applets shows how a D-latch can be realized using only 8 transistors (2 inverters and 2 T-gates), if both the clock and the inverted clock signal are available - a savings of 50% of transistors and therefore chip-area. If the inverted clock is not available, an additional inverter is needed to provide the control signal for the two T-gates, still with a savings of 10 transistors versus 16.

Click near the D input to select the data input value for the D-latch.
Click near the C (clock) or NC (inverted clock) input to toggle the current clock input value.

To simplify the circuit schematic, the C and NC wires are not drawn completely. Rather, the corresponding T-gate gate inputs are labeled with C or NC. Note that the input T-gate (on the left) is controlled by C, while the feedback T-gate (on top) is controlled by NC.

The current values for data input D, clock input C, and data output Q are plotted as waveforms on the bottom of the applet. This allows to demonstrate the data storage in the latch when the C input is '0'.
If you click anywhere else, the input voltages are not changed. However, simulation time is increased, and the waveforms are updated.

The function of the T-gate D-latch is very easy to understand. If the C input is '1', the input T-gate is conducting, and the data input value is connected to the first inverter input, which generates !D. The second inverter generates !!D = D, that is, the output Q equals D (the latch is transparent).

If the C input is switched to '0', the first T-gate is blocked while the feedback T-gate (whose R contact is connected to Q, which still equals D) is opened. Therefore, the circuit feeds its Q signal back to the first inverter (!Q) and to the second inverter !!Q=Q. That is, the value of Q is stored until the C input becomes '1' again.