~ELECTRONICS~

PART 3.2
 

The NAND gate with 2 inputs:

In the NAND gate the P-type transistors are connected in parallel between VCC and the output Y, while the N-type transistors are connected in series from GND to the output Y.

The NAND gate with 3 inputs:

The generalization of the 2-input NOR and NAND gates is obvious. As an example, the next applet shows a NAND gate with 3-inputs. As for the 2-input NAND, all (three) P-type transistors are connected in parallel between VCC and the output Y, while all N-type transistors are connected in series.

Again, the wires connecting the N-type transistors may have floating voltage levels when the transistors are nonconducting. That is no problem, because these wires are not connected to any transistor gate.

NOR gates with three and more inputs are constructed correspondingly - all P-type transistors are connected in series and the N-type transistors are connected in parallel between GND and the output Y.

However, the series connection of transistors implies longer propagation delay (especially for P-type transistors) and a voltage drop across the transistors. Therefore, NAND gates for actual CMOS cell libraries are usually limited to 4-inputs (4 N-type transistors in series) and NOR gates to 3-inputs (3 P-type transistors in series).

NAND and NOR gates with more inputs are realized as a combination of simpler gates with up to 3 (4) inputs.


PART 4