Part 3
Power consumption of the CMOS inverter
The previous discussion of the CMOS inverter shows
why CMOS logic has (almost) no static power dissipation: If the gate voltage
is either '1' or '0' there is no conducting path from VCC to GND, and there
is no static current through the inverter. In normal operation, the short-circuit
condition shown in the applet above arises only during the very short interval,
when the gate voltage is switched. Typical switching times for the gate
are around 2 ns, and the static current dissipation occurs only during
a fraction of this time (while the input voltage is near VCC/2). All other
basic CMOS gates have almost no static power dissipation as well.
But there is a dynamic current dissipation in
CMOS gates. The applet below illustrates this effect for the CMOS inverter.
The gate of a MOS transistor forms a small capacitor. Typical values for
the gate capacity are of order Cg = 10 fF. If the input of the inverter
is connected to VCC at time t1, this capacitor is charged (Charge
Q
= Cg * VCC). If the input is connected to GND at time t2 it
is discharged. The net effect of this is a very small current of I =
dQ/dt = (Cg * VCC)/(t2-t1).
However, due to several reasons the total current
drawn by a big CMOS chip, for example a microprocessor, can be quite large:
-
A modern microprocessor may contain about five million
transistors, that is, about one million gates. Typically, about one percent
of all gates switch during one cycle.
-
Operating frequencies are up to 200 MHz (cycle time
5 ns) at an operating voltage of VCC = 3.3V.
-
On VLSI chips, the wires connecting the gates have
a capacity Cw that is much bigger than the transistor gate capacities
Cg.
When switching an input, not only the transistor gate capacities but also
the whole wire needs to be charged or discharged: Ctotal=Cg+Cw.
Typical wire loads are about 1 pF
The total current resulting from the short-circuit
currents during switching is difficult to estimate. But the current resulting
from switching the input capacitance alone is quite large in the example:
I ~ #gates * (Ctotal*VCC) / dt = (1% * 1.000.000)
* (1pF * 3.3V) / 5ns = 6.6 A
On the other hand, the quiescent current in typical
static CMOS ICs is very small. For example, an 2K*8 bit CMOS SRAM dissipates
only 1 uA when idle.
The next applet illustrates the current dissipation
in the CMOS inverter. If the input voltage stays at '1' or '0', either
the N-type or the P-type transistor in nonconducting, and there is no current
through the inverter.
-
If the input is switched, the gates of the transistors
are charged/discharged. The applet draws a moving electron to illustrate
this.
-
If the input is switched, the input voltage passes
the region near VCC/2, where both transistors are conducting. That is,
during a very short time after each switching, there is a direct (short-circuit)
current through the inverter. This current again is shown by a moving electron.
The power consumption of static CMOS logic is
therefore directly proportional to switching frequency.
